Model T System bus: Difference between revisions
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The system bus differs on the different models but are very close | The system bus differs on the different models but are very close electrical wise. | ||
<table> | The M100 has a 40-pin DIP socket while M102 and T200 have a 20x2 (2.54mm/0.1") pin array. | ||
<tr><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr> | |||
The differnet pin arangements cause the pins of the 100 to be numbered differently to the 102/200. | |||
<table border="1"> | |||
<tr><td></td><td>100</td><td>102</td><td>200</td></tr> | |||
<tr><td>1</td><td>VDD</td><td>VDD</td><td>VDD</td></tr> | |||
<tr><td>2</td><td>GND</td><td>VDD</td><td>VDD</td></tr> | |||
<tr><td>3</td><td>AD0</td><td>GND</td><td>GND</td></tr> | |||
<tr><td>4</td><td>AD2</td><td>GND</td><td>GND</td></tr> | |||
<tr><td>5</td><td>AD4</td><td>AD0</td><td>AD0</td></tr> | |||
<tr><td>6</td><td>AD6</td><td>AD1</td><td>AD1</td></tr> | |||
<tr><td>7</td><td>A8</td><td>AD2</td><td>AD2</td></tr> | |||
<tr><td>8</td><td>A10</td><td>AD3</td><td>AD3</td></tr> | |||
<tr><td>9</td><td>A12</td><td>AD4</td><td>AD4</td></tr> | |||
<tr><td>10</td><td>A14</td><td>AD5</td><td>AD5</td></tr> | |||
<tr><td>11</td><td>GND</td><td>AD6</td><td>AD6</td></tr> | |||
<tr><td>12</td><td>/RD</td><td>AD7</td><td>AD7</td></tr> | |||
<tr><td>13</td><td>IO/M</td><td>A8</td><td>A8</td></tr> | |||
<tr><td>14</td><td>ALE</td><td>A9</td><td>A9</td></tr> | |||
<tr><td>15</td><td>CLK</td><td>A10</td><td>A10</td></tr> | |||
<tr><td>16</td><td>/A</td><td>A11</td><td>A11</td></tr> | |||
<tr><td>17</td><td>INTR</td><td>A12</td><td>A12</td></tr> | |||
<tr><td>18</td><td>GND</td><td>A13</td><td>A13</td></tr> | |||
<tr><td>19</td><td>RAMRST</td><td>A14</td><td>A14</td></tr> | |||
<tr><td>20</td><td>NC</td><td>A15</td><td>A15</td></tr> | |||
<tr><td>21</td><td>NC</td><td>GND</td><td>GND</td></tr> | |||
<tr><td>22</td><td>NC</td><td>GND</td><td>GND</td></tr> | |||
<tr><td>23</td><td>GND</td><td>/RD</td><td>/RD</td></tr> | |||
<tr><td>24</td><td>INTA</td><td>/WR</td><td>/WR</td></tr> | |||
<tr><td>25</td><td>/RST</td><td>IO/M</td><td>IO/M</td></tr> | |||
<tr><td>26</td><td>/YO</td><td>S0</td><td>S0</td></tr> | |||
<tr><td>27</td><td>S1</td><td>/ALE</td><td>ALE</td></tr> | |||
<tr><td>28</td><td>S0</td><td>S1</td><td>S1</td></tr> | |||
<tr><td>29</td><td>/WR</td><td>CLK</td><td>CLK</td></tr> | |||
<tr><td>30</td><td>GND</td><td>Y0</td><td>/IOCONT</td></tr> | |||
<tr><td>31</td><td>A15</td><td>/A</td><td>E</td></tr> | |||
<tr><td>32</td><td>A13</td><td>/RESET</td><td>RESET</td></tr> | |||
<tr><td>33</td><td>A11</td><td>INTR</td><td>INTR</td></tr> | |||
<tr><td>34</td><td>A9</td><td>INTA</td><td>/INTA</td></tr> | |||
<tr><td>35</td><td>DA7</td><td>GND</td><td>GND</td></tr> | |||
<tr><td>36</td><td>DA5</td><td>GND</td><td>GND</td></tr> | |||
<tr><td>37</td><td>DA3</td><td>/RAMRST</td><td>/RAMRST</td></tr> | |||
<tr><td>38</td><td>DA1</td><td>NC</td><td>NC</td></tr> | |||
<tr><td>39</td><td>GND</td><td>NC</td><td>NC</td></tr> | |||
<tr><td>40</td><td>VCC</td><td>NC</td><td>NC</td></tr> | |||
</table> | </table> | ||
[[Category:Model T Developer Reference]] | |||
Revision as of 11:25, 21 February 2009
The system bus differs on the different models but are very close electrical wise.
The M100 has a 40-pin DIP socket while M102 and T200 have a 20x2 (2.54mm/0.1") pin array.
The differnet pin arangements cause the pins of the 100 to be numbered differently to the 102/200.
| 100 | 102 | 200 | |
| 1 | VDD | VDD | VDD |
| 2 | GND | VDD | VDD |
| 3 | AD0 | GND | GND |
| 4 | AD2 | GND | GND |
| 5 | AD4 | AD0 | AD0 |
| 6 | AD6 | AD1 | AD1 |
| 7 | A8 | AD2 | AD2 |
| 8 | A10 | AD3 | AD3 |
| 9 | A12 | AD4 | AD4 |
| 10 | A14 | AD5 | AD5 |
| 11 | GND | AD6 | AD6 |
| 12 | /RD | AD7 | AD7 |
| 13 | IO/M | A8 | A8 |
| 14 | ALE | A9 | A9 |
| 15 | CLK | A10 | A10 |
| 16 | /A | A11 | A11 |
| 17 | INTR | A12 | A12 |
| 18 | GND | A13 | A13 |
| 19 | RAMRST | A14 | A14 |
| 20 | NC | A15 | A15 |
| 21 | NC | GND | GND |
| 22 | NC | GND | GND |
| 23 | GND | /RD | /RD |
| 24 | INTA | /WR | /WR |
| 25 | /RST | IO/M | IO/M |
| 26 | /YO | S0 | S0 |
| 27 | S1 | /ALE | ALE |
| 28 | S0 | S1 | S1 |
| 29 | /WR | CLK | CLK |
| 30 | GND | Y0 | /IOCONT |
| 31 | A15 | /A | E |
| 32 | A13 | /RESET | RESET |
| 33 | A11 | INTR | INTR |
| 34 | A9 | INTA | /INTA |
| 35 | DA7 | GND | GND |
| 36 | DA5 | GND | GND |
| 37 | DA3 | /RAMRST | /RAMRST |
| 38 | DA1 | NC | NC |
| 39 | GND | NC | NC |
| 40 | VCC | NC | NC |
