5MHZ upgrade for Model T
Updated January 2024 work in progress!
This page shares the latest in a long sequence of "clock doubler" boards for the 80C85 used in the Model T computers.
Status
* latest board is V4.6; Boards received and verified for M100. * Clock doubler power reduced enough to consider it "done"
Goals
* support for all Model T computers - M100, T102, T200, PC-8201, PC-8300, M10, KC-85 * buildable with moderate effort and skill * minimal and reversible modification to the computer
Features
* software switchable speed up for compatibility * settable power-up default speed, 1x or 2x * hardware driven 1x slowdown function (needed for T200) * accelerated RAM timing signal (needed for M100, T102, NEC, KC-85, M10) * single sided component placement * 3 different PCB designs, optimized for fit in the specific laptop. * surface mount logic, leaded through-hole passives * low power consumption
PCB, Schematic, Design Files
note: revised board packages are released below.
PCB version 4.61 for M100
Improved version, dual footprint for buffer Note: usable in NEC PC-8201
Gerbers Board images Schematic image Eagle design files BOM
PCB version 4.61 for T200
First release for T200; surface mount caps/resistors, crystal mounted under PCB No need for A* circuit Includes CL circuit
Gerbers Board images Schematic image Eagle design files BOM
PCB version 4.61 for M10
First release for M10; sized to fit restricted space. Dual footprint buffer. Note: usable in NEC PC-8201
Gerbers Board images Schematic image Eagle design files BOM
PCB version 4.61 for T102
First release for T102; sized to fit restricted space. Dual footprint buffer. Note: usable in NEC PC-8201
Gerbers Board images Schematic image Eagle design files BOM
Prior board releases
These files are kept available for reference.
PCB version 4.6 for M100
Initial release; only works for M100, not M10 as originally thought. don't use this one; recommend to use V4.61 below.
Gerbers Board images Schematic image Eagle design files BOM
Since OSHPARK is so clumsy in dealing with PCB revisions (basically you can't remove a bad file design once shared), I've decided to just post PCB gerber files and schematics here. That way I can control issues that I find and always have the corrected files available. IF files are posted at OSHPark it won't be by me, so no promises.
Clock Doubler build how-to
Version 4.6 PCB involves some pretty fine SMT soldering. This how-to doc is based on V4.4 PCB so is a little out of date. I will post an update soon.
Build how-to
Installation how-to
As I test and more-or-less land on a reasonable upgrade process, I will post instruction files here If you have any questions, please get in touch with me at Twospruces at --the google mail service.
M100
M100 install how-to
Olivetti M10
TBD
Tandy 200
TBD
Tandy 102
TBD
NEC PC-8201
TBD
Olivetti M10
TBD
Bill of Materials
...of course you need to order a PCB using the Gerbers. I use JLCPCB; they are great and it is really easy. Just upload the gerbers and order.
Note: BOMs are specific to the board type. Download along with the board files. They are mostly the same but T200 is notably different.
Technical discussion
Power Consumption
In general, running at 5MHz consumes more power than 2.5MHz operation. In my experience, the speed increase tends to consume ~25mA of power supply current. Some of that current is due to the faster operation of the M100 (~15mA) and the remainder is due to the addition of the clock doubler board (~10mA).
The onboard oscillator circuit consumes more power all the time, as it replaces the oscillator in the 80C85. The flip flops, clock divider and clock mux on the 1x2x board also consume more power.
In M100 for example, if the typical current is 47mA, - adding in the 1x2x board (V4.61) increases current to 57mA at 2.5 MHz. - 5MHz operation drives up the current to 73mA or so.
The V4.6 1x2x clock doubler board consumes 10mA at 2.5MHz and 12mA at 5MHz. The M100 itself consumes an additional 15mA to speed up to 5MHz.
Just for information, I have a CPLD based clock doubler board that only consumes 4mA at 5MHz.
My personal feeling is that it is much better to have the option to run fast than to worry about consuming more battery. To each their own.
M100
In the Model 100, running at 2x clock rate requires a solution to 2 issues in general.
1. The main ROM is typically too slow 2. The SRAM modules may also be too slow.
Either of these issues may impair operation at 5MHz. OR - you might get lucky and it runs fine as is.
Speeding up the Main ROM
In the M100 technical reference, there is a comment that states the main ROM has 600nsec timing. Original ROMs were this slow; newer ones were faster. If after installation and trial, you believe your main ROM is too slow, this can be easily overcome by swapping in an EPROM. There are several solutions for this - for example there are adapter boards that convert the custom M100 main ROM pinout to standard 27C256. I recommend using a 200nsec or faster EPROM. No need to change the binary image, but you can always convert to T102 ROM for the bug fixes.
Speeding up the SRAM
On early M100s the system RAM is also (barely) too slow. Early RAM modules were 250nsec SRAM. Take a look at your SRAM... if they are -25 then they are too slow. If they are -20 or -15, you are probably ok.
The original A* signal in the standard M100/T102 design, is used to minimize SRAM power by disabling the SRAM when no read/write is occurring. This is actually very important. The longer the SRAM stays "on" the more power it consumes. In a battery laptop, you want to shut of the SRAM as much as possible. However, the timing of the A* signal is quite delayed in the CPU read/write cycle. A* is driven by the /RD and /WR signals.
To make slow SRAM work at 5MHz, you need to create an A* signal that enables the SRAM a bit earlier in the CPU cycle. This special A* signal needs to be wired into the M100. This involves cutting one track and soldering one wire.
The clock doubler PCB includes a generation of a replacement A* signal, which allows the slower SRAM to work at 5MHz.
T102
T102 installation is very similar to the M100. I have not however observed any problem with Main ROM speed; it seems that the T102 benefits from being built later, and hence has faster main ROMs. T102 does however require modified A* timing just like the M100.
T200
T200 installation is simpler than M100/T102, in that there is no issue related to Main ROM. SRAM speed can be an issue. On the Memory board (the board that has the option RAM and ROM sockets) there are 3 8k SRAMs for Bank 1. If these rams are 200nsec (-20) rated, the could be too slow.
T200 does have one new gotcha. The real time clock chip RP5C01 is really slow and cannot run at 5MHz. Period. So, we need another solution.
Dealing with slow SRAM
There isn't an easy way to accelerate the SRAM timing like was done for the M100/T102/NEC/M10 etc. Replacing the SRAM chips is a lot of work. An alternative would be to (1) disable the onboard SRAM and (2) add an SRAM card that can provide all 3 banks with fast SRAM. Such a board does now exists! I have a design which is a modified 2x24kB module that now offers 3x24kB of fast sram, so you can simply disable the slow original SRAM. So, if you have 200nsec SRAM, you could consider this 3x24kB module. It is easy to install.
Slowing down to use the RTC
The answer is to actually disable 5MHz operation when the CPU is accessing the real time clock chip. Thankfully, there is a pretty easy fix. The clock doubler PCB has a special input signal that, when low, disables 2x mode. Addition of a single wire to connect the "CL" signal at a specific location on the T200 motherboard, to this input allows the T200 to automatically slow down only when the RP5C01 is being selected.
Low Profile
Building this for installation in T200 requires that the height of the board over the CPU be kept to a minimum. Make sure all avenues for minimizing height are utilized. Consider using surface mount caps for example to keep the profile to a minimum. Ideally the SMT chips should be the tallest components on the board, and the board should be mounted flush to the CPU.
NEC PC-8201
I have not yet done an actual install, but I expect it will have the same issues as M100.
Expect the Main ROM may be slow, and needs a 27C256 upgrade. Expect there could be slow SRAM modules, and needs a new A* signal.
NEC PC-8300
I have not yet done an actual install, but I expect the machine is compatible with 5MHz operation with no problem with Main ROM or SRAM timing.
Olivetti M10
I have not yet done an actual install, but I expect it will have the same issues as M100.
Expect the Main ROM may be slow, and needs a 27C256 upgrade. Expect there could be slow SRAM modules, and needs a new A* signal.
Kyocera KC-85
I have not yet done an actual install (because I don't have a KC-85!, but I expect it will have the same issues as M100.
Expect the Main ROM may be slow, and needs a 27C256 upgrade. Expect there could be slow SRAM modules, and needs a new A* signal.
Software control of the clock doubler
To control the clock rate of the laptop, the following BASIC commands are used.
OUT85,0 sets to 2.5MHz OUT85,1 sets to 5MHz
Easy to remember! 8085
What about compatibility with REX#/REXCPM?
REX# and REXCPM from November 2021 are built and tested compatible with 5MHz. In fact my test station runs at 5MHz. If you have an earlier REX#/REXCPM, contact me to discuss what to do.
NSC800 / CP/M @ 5MHz
For M100 with NSC800, contact me for a solution. This would of course be a dedicated CP/M machine with REXCPM installed.
Hardware Compatibility Issues @ 5MHz
As issues are identified, they will get listed here.
So, I have noticed that in some cases things may not work 100% at 5MHz. I'll describe what I observe here.
Main ROM speed in M100
This has been mentioned above. I think the Main ROMS with the original custom pinout are the slow ones (the ones marked "SHARP"). Not all are too slow however. I think around 25-30% of them are ok to work at 5MHz, based on my count of the upgrades I have done on M100.
Serial Port Performance
I have observed that the serial port may not work ideally at 5MHz. In about 1/2 of my M100/M10/PC8201 fleet, the serial port cannot access a TPDD at 5MHz. So far I've not observed the issue on T102, T200. It's a bit weird because the serial port still operates; a terminal session for example can exchange characters without issue. So, I don't know what exactly breaks on the serial port, but certainly something is happening. The answer is to switch to 1x mode if you have a problem.
Video Performance
I've noticed 2 issues can crop up with the LCD.
First issue: some LCD driver chips appear to begin to "miss dots" at 2x mode. I attribute this to marginal data writes at high speed, which makes sense. I've seen this issue on about 10% of the LCDs so far.
Second issue: a really bizarre thing happens to the display when you run "STAR.CO" at 5MHz. The LCD data is displayed horizontally garbled. It's hard to describe, but dots appear to be shifted horizontally relative to what would be expected. This issue occurs on ALL conversions I have tried, so it is not related to a marginal LCD. There is something about how the LCD is being accessed by "STAR.CO". Maybe what is happening will become more clear over time.
Software Compatibility Issues @ 5MHz
As issues are identified, they will get listed here.
FAQ
As this is tried I'm sure questions and comments will arise. We can capture useful information here. Thanks.
Q. Can I buy this assembled and tested from you? A. No, unfortunately. I have no way of testing it other than to install it. I think it is best to consider this a DIY project.
