View source for Model T System bus

The system bus differs on the different models but are very close electrical wise.

The M100 has a 40-pin DIP socket while M102 and T200 have a 20x2 (2.54mm/0.1") pin array.

The different pin arrangements cause the pins of the 100 to be numbered differently to the 102/200.

<table border="1">
<tr><td></td><td>100</td><td>102</td><td>200</td></tr>
<tr><td>1</td><td>VDD</td><td>VDD</td><td>VDD</td></tr>
<tr><td>2</td><td>GND</td><td>VDD</td><td>VDD</td></tr>
<tr><td>3</td><td>AD0</td><td>GND</td><td>GND</td></tr>
<tr><td>4</td><td>AD2</td><td>GND</td><td>GND</td></tr>
<tr><td>5</td><td>AD4</td><td>AD0</td><td>AD0</td></tr>
<tr><td>6</td><td>AD6</td><td>AD1</td><td>AD1</td></tr>
<tr><td>7</td><td>A8</td><td>AD2</td><td>AD2</td></tr>
<tr><td>8</td><td>A10</td><td>AD3</td><td>AD3</td></tr>
<tr><td>9</td><td>A12</td><td>AD4</td><td>AD4</td></tr>
<tr><td>10</td><td>A14</td><td>AD5</td><td>AD5</td></tr>
<tr><td>11</td><td>GND</td><td>AD6</td><td>AD6</td></tr>
<tr><td>12</td><td>/RD</td><td>AD7</td><td>AD7</td></tr>
<tr><td>13</td><td>IO/M</td><td>A8</td><td>A8</td></tr>
<tr><td>14</td><td>ALE</td><td>A9</td><td>A9</td></tr>
<tr><td>15</td><td>CLK</td><td>A10</td><td>A10</td></tr>
<tr><td>16</td><td>/A</td><td>A11</td><td>A11</td></tr>
<tr><td>17</td><td>INTR</td><td>A12</td><td>A12</td></tr>
<tr><td>18</td><td>GND</td><td>A13</td><td>A13</td></tr>
<tr><td>19</td><td>RAMRST</td><td>A14</td><td>A14</td></tr>
<tr><td>20</td><td>NC</td><td>A15</td><td>A15</td></tr>
<tr><td>21</td><td>NC</td><td>GND</td><td>GND</td></tr>
<tr><td>22</td><td>NC</td><td>GND</td><td>GND</td></tr>
<tr><td>23</td><td>GND</td><td>/RD</td><td>/RD</td></tr>
<tr><td>24</td><td>INTA</td><td>/WR</td><td>/WR</td></tr>
<tr><td>25</td><td>/RST</td><td>IO/M</td><td>IO/M</td></tr>
<tr><td>26</td><td>/YO</td><td>S0</td><td>S0</td></tr>
<tr><td>27</td><td>S1</td><td>/ALE</td><td>ALE</td></tr>
<tr><td>28</td><td>S0</td><td>S1</td><td>S1</td></tr>
<tr><td>29</td><td>/WR</td><td>CLK</td><td>CLK</td></tr>
<tr><td>30</td><td>GND</td><td>Y0</td><td>/IOCONT</td></tr>
<tr><td>31</td><td>A15</td><td>/A</td><td>E</td></tr>
<tr><td>32</td><td>A13</td><td>/RESET</td><td>RESET</td></tr>
<tr><td>33</td><td>A11</td><td>INTR</td><td>INTR</td></tr>
<tr><td>34</td><td>A9</td><td>INTA</td><td>/INTA</td></tr>
<tr><td>35</td><td>DA7</td><td>GND</td><td>GND</td></tr>
<tr><td>36</td><td>DA5</td><td>GND</td><td>GND</td></tr>
<tr><td>37</td><td>DA3</td><td>/RAMRST</td><td>/RAMRST</td></tr>
<tr><td>38</td><td>DA1</td><td>NC</td><td>NC</td></tr>
<tr><td>39</td><td>GND</td><td>NC</td><td>NC</td></tr>
<tr><td>40</td><td>VCC</td><td>NC</td><td>NC</td></tr>
</table>

[[Category:Model T Developer Reference]]