NSC800 Conversion: Difference between revisions

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Work in progress!
Work in progress!


[[Image:NSC800.png||center]]<br/>
[[Image:NSC800.jpg||center]]<br/>




== What is this all about? ==
== What is this all about? ==


External serial bidirectional communication on the Model 100 today is limited to (1) the RS-232 port and (2) the modem port, both of which use the single UART in the computer.
Motivated by 2 things
* discovery (to me) of the NSC800 Z80 processor that is 80C85 like
* continuing to work in the direction of CP/M


This hack enables the BCR port to send and receive half duplex serial TTL signals.  The BCR port is already set up for TTL receive function as this is used for the Bar Code Reader function.  So this hack provides facility to transmit as well.  In addition I provide some software routines that demonstrate the capability.
I have invested some time and effort in developing a conversion that supports NSC800 operation in the M100, both for standard BASIC use, as well as CP/M (in conjunction with REXCPM).  Partly this has been motivated simply by curiosity.  However, in CP/M it actually broadens the software applicability since quite a bit of CP/M software is Z80.


BCR port serial TTL is supported in Model 100 CP/M as well as with the VT100 Driver, for use with VT100 Terminal or other VT100 CRT solution.
If you have an interested in doing this conversion please get in touch with me at Twospruces at --the google mail service.


Get in touch with me at Twospruces at --the google mail service.
There are 2 areas of change that are needed.
Firstly you have to adapt the NSC800 to the 80C85 socket.  There are a couple of tradeoffs to make. 
Secondly, the NSC800 needs to use a slightly different Main ROM.


== Acknowledgements ==
To get started on this project, one can leverage the work done in the past.  In fact an NSC800 conversion for 80C85 was posted back in the early 80s for S100 computers equipped with an 8080/8085 processor board.  The information is posted below, from
Microsystems September 1984.


I would like to acknowledge and thank those that have contributed to the project:
[[Media:NSC800 conversion1.JPG|NSC800 conversion1.JPG]]


'''Philip Avery''' - for efforts with CP/M and attached Video using the VT100 Adapter
[[Media:NSC800 conversion2.JPG|NSC800 conversion2.JPG]]


This article lists considerations; from my work in M100 the things that any adapter has to deal with are listed below.


==Improved BCR Hack==
  1.  Inversion of the interrupt signals
  2.  Conversion of the 50/50 duty cycle RST7.5 signal to a 100 usec low pulse (NSC800 is level triggered not edge).
  3.  4.9152 MHZ clock generation circuitry.
  4.  And in the case of a dual processor conversion, certain NSC800 signals are not tri-state in RESET.


===CP/M Status===
Note:  it seems that the M100 RAM/ROM and REX are all tolerant of the short opcode fetch read/write cycle.  So, no wait state generator appears to be needed.
* currently supported in CPM210/410 as CASS video option


=== Supported Models ===
While I have implemented both a DUAL 80C85/NSC800 CPU adapter, and a SINGLE NSC800 CPU conversion, I prefer the single conversion for it's simplicity.
*  TRS-80 Model 100
*  a hardware hack for T102 is likely however not explored at this time
*  a similar hack should be possible for all ModelT versions.


=== The Hardware Modification ===
== 1CPU NSC800 conversion PCB ==


=== The Software ===
The current schematic is here.  So far so good.  May change.


[[Image:1CPU_schem.PNG|1CPU_schem.PNG]]


Layout is being optimized.  Current layout is here as an example, but this board is not done yet.
Gives you a sense for what's involved.


The BOM is pretty short
  - PCB
  - NSC800 CPU  3MHz variety  (UTsource is good)
  - socket for M100 main board
  - 74HC04 buffer/inverter
  - 4.9152 MHz Oscillator + 2x 27pf caps
  - low profile pin arrangement for connecting PCB to M100 80C85 socket
  Note:  due to height restrictions, you have to solder the NSC800 processor to the adapter (trying to resolve this)






==Original BCR Hack==
[[Image:1CPU_pri.PNG|1CPU_pri.PNG]]


===CP/M Status===
* currently supported in CPM210/410 as CASS video option


=== Supported Models ===
[[Image:1CPU_sec.PNG|1CPU_sec.PNG]]
*  TRS-80 Model 100
*  a hardware hack for T102 is likely however not explored at this time
*  a similar hack should be possible for all ModelT versions.






=== The Hardware Modification ===
== Modified M100 Main ROM ==


'''UDPATE:  an improved implementation is being tested, which is more universal.  SOD pin is available on 80C85 but not Z80.  As such, there is a change where we can utilize /Y1 signal...making this hack accessible with both NSC800 and 80C85. '''
As mentioned, since the interrupt control mechanisms in NSC800 are slightly different, the M100 main ROM needs to be patched to support NSC800.


The NSC800 patch needs extra code space to be created in the ROM.  To do that, an original patch has been verified that creates a block of unused space in the main ROM as published by Microsoft.


The core of the modification is to connect pin 3 of the BCR port to the SOD output of the CPU. This is accomplished by adding a single wire to the PCB.
[[File:base_patch.zip|base_patch.zip]]


  This page details the hardware change required to transmit at 57600 baud with minimal changes.
Once this base patch is applied to the ROM, you have space now for the next set of patches, here.
  It can be demonstrated that, in the M100, both serial Tx and Rx is possible at 57600 over the BCR port.


  Tx and Rx at higher speeds is more challenging.  Tx speeds of up to 128000 baud have been demonstrated.
  Transmission at this rate requires disconnection of the cassette port Tx filter at C63.
  If you remove C63 you get better signal quality for TTL serial, but the cassette port is no longer usable.
  If, like me, you never use the cassette port they it may not be a big deal.


The following image shows the modification to the M100 Cassette/BCR port circuitry.
[[File:patch_nsc800.zip|patch_nsc800.zip]]


[[Image:ckt2.png||center]]<br/>


Here we see a strap added from pin 12 of M34 to pin 3 of the BCR port, defining this pin as Tx data.
All these patches rolled up into a binary:  (here I used the T102 base ROM as the starting point)


The following image shows the placement of the strap on the secondary side of the M100 PCB.
[[File:M102_nsc800.zip|M102_nsc800.zip]]




[[Image:layout2.png||center]]<br/>
These are what I use today.  If I find bugs I will post updates.
 
=== The Software ===
 
As mentioned, the use of the BCR port to send TTL data to the external CRT is supported in Model 100 CP/M, as well as by using the VT100 Driver, which integrates the external CRT with BASIC, based on Microsoft Disk BASIC for the Model 100.
 
Additionally, I include some code here as examples.
 
==== 57600 Baud Routines ====
 
Currently both CP/M and my own VT100 driver user 57600, using the modification posted here.
 
The following code can be compiled, and run in Model 100 to demonstrate transmission between 2 machines at 57600.
 
Tx routine:
    [[Media:keysnd_57600.zip|keysnd_57600.asm]]
Rx routine:
    [[Media:bcrx_57600.zip|bcrx_57600.asm]]
 
 
I may have done the M100 <--> M100 testing using an improved circuit (IE remove C63).  I'm not sure; if you do try this experiment keep it in mind that the Tx signal quality is better if you pull C63.  This of course makes the cassette port useless.
 
==== Higher speed Tx Routines ====
 
Faster transmission is possible; both 115600 and 128000 baud have been demonstrated.  The core Tx routines are provided here.
 
for Tx at 57600 baud:
    [[Media:bcrtx_57600.zip|bcrtx_57600.asm]]
for Tx at 115600 baud:
    [[Media:bcrtx_115600.zip|bcrtx_115600.asm]]
for Tx at 128000 baud:
    [[Media:bcrtx_128000.zip|bcrtx_128000.asm]]
 
 
 
==== Timing for 57600 Baud ====
 
Since the processor is 100% busy reading in bits during Rx functions, the requirement for the BCR port receiver is to read and place the byte into memory before the stop bit is completed.  The faster the Rx can process the received byte, the faster the link rate can be.  At 57600 baud that is about 17 microseconds.  Typical processor instruction time is between 1.2 and 1.6 microseconds, so this is about 10-12 instructions max (42.65 clock cycles).
I think that is enough time to write to memory and increment a counter or a parity, and a jump or 2.
57600 baud then looks feasible, even for large memory transfers so long as the buffer can be continuously written to without interruption while the PC is sending data.  It also means that the RS-232 port could run flat-out at 5.7 kBytes/sec in the Rx direction.
In the Tx direction it similar, but it takes a small amount of time to prepare the data before sending the start bit and following data bits.  I think it is probably better than 5.5 kbytes/sec.
 
For CP/M and REXCPM backup/restore this means
  4MB backup restore time could be about 12 minutes @57600 baud
    -- assuming "large packet support" on LaddieAlpha, and direct writes to block RAM.
 
 
What about 115600 or 128000 baud?  While the Tx side has been shown to work, the Rx side is the challenge.
Challenge 1.  The M100 ROM requires an initial interrupt and then 3 jumps to get to the RST6.5 hook.  The M100 has to make it to the RX code before the data arrives.  This places a practical limit of 57600 on the rate.  76800 is too fast.  However if an option ROM was used this could potentially be sped up.
 
A quick look at BCRX.ASM above suggests the RX bit reception time could be reduced to 29 clock cycles, supporting ~85000 baud.
 






[[Category:Model T Hardware]]
[[Category:Model T Hardware]]

Revision as of 09:25, 6 October 2020

Work in progress!

NSC800.jpg



What is this all about?

Motivated by 2 things

  • discovery (to me) of the NSC800 Z80 processor that is 80C85 like
  • continuing to work in the direction of CP/M

I have invested some time and effort in developing a conversion that supports NSC800 operation in the M100, both for standard BASIC use, as well as CP/M (in conjunction with REXCPM). Partly this has been motivated simply by curiosity. However, in CP/M it actually broadens the software applicability since quite a bit of CP/M software is Z80.

If you have an interested in doing this conversion please get in touch with me at Twospruces at --the google mail service.

There are 2 areas of change that are needed. Firstly you have to adapt the NSC800 to the 80C85 socket. There are a couple of tradeoffs to make. Secondly, the NSC800 needs to use a slightly different Main ROM.

To get started on this project, one can leverage the work done in the past. In fact an NSC800 conversion for 80C85 was posted back in the early 80s for S100 computers equipped with an 8080/8085 processor board. The information is posted below, from Microsystems September 1984.

NSC800 conversion1.JPG

NSC800 conversion2.JPG

This article lists considerations; from my work in M100 the things that any adapter has to deal with are listed below. 

  1.  Inversion of the interrupt signals
  2.  Conversion of the 50/50 duty cycle RST7.5 signal to a 100 usec low pulse (NSC800 is level triggered not edge).
  3.  4.9152 MHZ clock generation circuitry.
  4.  And in the case of a dual processor conversion, certain NSC800 signals are not tri-state in RESET.

Note: it seems that the M100 RAM/ROM and REX are all tolerant of the short opcode fetch read/write cycle. So, no wait state generator appears to be needed.

While I have implemented both a DUAL 80C85/NSC800 CPU adapter, and a SINGLE NSC800 CPU conversion, I prefer the single conversion for it's simplicity.

1CPU NSC800 conversion PCB

The current schematic is here. So far so good. May change.

1CPU_schem.PNG

Layout is being optimized. Current layout is here as an example, but this board is not done yet. Gives you a sense for what's involved.

The BOM is pretty short 

  - PCB
  - NSC800 CPU  3MHz variety  (UTsource is good)
  - socket for M100 main board
  - 74HC04 buffer/inverter
  - 4.9152 MHz Oscillator + 2x 27pf caps
  - low profile pin arrangement for connecting PCB to M100 80C85 socket
  Note:  due to height restrictions, you have to solder the NSC800 processor to the adapter (trying to resolve this)


1CPU_pri.PNG


1CPU_sec.PNG


Modified M100 Main ROM

As mentioned, since the interrupt control mechanisms in NSC800 are slightly different, the M100 main ROM needs to be patched to support NSC800.

The NSC800 patch needs extra code space to be created in the ROM. To do that, an original patch has been verified that creates a block of unused space in the main ROM as published by Microsoft.

File:Base patch.zip

Once this base patch is applied to the ROM, you have space now for the next set of patches, here.


File:Patch nsc800.zip


All these patches rolled up into a binary: (here I used the T102 base ROM as the starting point)

File:M102 nsc800.zip


These are what I use today. If I find bugs I will post updates.

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